Wireless Core
Introduction
The Wireless Core is implemented as a custom network stack. Its purpose is to facilitate transceiver setup, making it possible to optimize performance for data rate, latency and power consumption. It manages wireless functionalities within the SDK and is controllable via its top-level API, the Wireless Core API. It is compatible with the SR1010, SR1020 and SR1120 transceivers. Most documentation sections apply to all transceiver models, but when exceptions arise, tabs with specific model numbers are used to highlight them.
Several concepts must be fully understood before delving into the design of a network with the Wireless Core. This documentation describes all those concepts, provides tips on how to design an optimal schedule and gives guidelines on how to optimize resources utilization.
Concepts
- Time Division Multiple Access
- Network
- Schedule
- Frequency Switching
- Addressing
- Connection
- Timeslot Ownership
- Remote Node
- Channel
- Stream Types
- Auto-Reply
- Timeslot Events
- Synchronization Methods
- Dual Radio
- Topology
- Concurrency
- Sleep Modes
- Modulation
- Symbol Averaging / Chip Repetition
- Forward Error Correction (FEC) Ratio
- Inter-Symbol Interference (ISI) mitigation
- Over-The-Air Chip Rate
- Stop and Wait
- Credit-Based Flow Control
- Frame Fragmentation
- Fallback Mode
- Link Throttling
- Connection Priority
- Auto-Sync
- Latency optimization
- Frame Structure
- Certification Mode
- Data Validation
MCU Requirements
Schedule Design Consideration
Latency
- Wireless Latency
- Components
- Formulas
- Non-Deterministic Nature
- Inter-Opportunity Gap
- Optimized Latency Feature
- Initial Connection Latency (Fast Sync)
- CCA Timing
- Post-RX Decode Time
- ACK Turnaround Time
- RX Processing Time
- Priority Blocking
- Retransmission Impact (Stop-and-Wait ARQ)
- Throttling
- Fragmentation
- Worked Example: Bidirectional HID (64-byte payload)