Power Consumption Optimizations

In this section, some strategies are outlined for reducing power consumption.

  • Reduce the transceiver’s input voltage:

    Keep the supply voltage as low as possible. The transceiver’s supply voltage can range from 1.8V to 3.3V.

  • Avoid use of firmware delay:

    A software delay keeps the CPU active, thus needlessly consumes power. Try to use timer peripherals instead and apply a power saving method while waiting for its period to end.

  • Use non-blocking transfer:

    The user must always try to use non-blocking transfers with the help of DMA peripherals when using a communication interface (SPI, I2C, USART, etc.). Instead of blocking the CPU waiting on a transfer complete event, a non-blocking transfer allows the MCU to do other processing tasks or go into sleep mode.

  • Change the transceiver’s sleep level:

    If the target data rate allows for a deeper sleep level, do not hesitate to use the transceiver’s shallow or deep sleep levels. Those sleep levels decrease the current consumption of the transceiver when not transmitting or receiving by shutting down its internal DC/DC converter. See the Sleep Modes section for further details on sleep modes.

  • Disable application logging:

    If possible, disable all logging. Don’t forget to disable unused serial peripherals accordingly (e.g.: UART).

  • Keep unused peripherals disabled:

    Do not initialize unused peripherals to prevent them from consuming any power.

  • Reduce peripherals clock speed:

    Lowering the clock speed of active peripherals (e.g.: SPI, UART, GPIOs) will decrease power consumption. For instance, if your application does not require a high data throughput and has loose or no latency requirements, lower the clock speed of the SPI peripheral controlling the transceiver. The default speed of 40MHz is not always required.

  • Use link throttling:

    The link throttling allows the user to define an alternative, lower power mode of operation. If the application can reduce its data generation rate, link throttling can be activated to reduce the Wireless Core footprint and free up CPU cycles. See the Link Throttling section for more details on this feature.