Hardware Platform Requirements

This section aims to help users choose an MCU that has all the necessary peripherals required to satisfy application requirements. Processing performance can then be evaluated on the ported design.

MCU Resources

An MCU with the following resources is required to interface with SPARK transceivers and the Wireless Core:

Core Type:

  • ARM Cortex-M

MCU features:

  • 1x GPIO pin to drive the transceiver’s Reset pin

  • 1x GPIO pin to serve as the SPI Chip Select

  • 1x External interrupt pin for servicing the transceiver’s IRQs

  • 1x SPI/QSPI bus controller configured as master

  • 1x Software interrupt

  • 2x DMA channels linked to the SPI peripheral

  • 1x Free-running timer

Warning

The dual radio feature is not supported by the EVK1.4 hardware.

Note

The CPU load is expected to be approximately 1.5 times greater than single radio (varies depending on application).

See Wireless Core Dual Radio documentation

Core Type:

  • ARM Cortex-M

MCU features:

  • 2x GPIO pin to drive the transceiver’s Reset pin

  • 2x GPIO pin to serve as the SPI Chip Select

  • 2x External interrupt pin for servicing the transceiver’s IRQs

  • 2x SPI bus controller configured as master

  • 1x Software interrupt

  • 4x DMA channels for the SPI data transfers between the MCU and the transceiver

  • 1x Free-running timer

  • 1x 16-bit (minimum) hardware timer running at +/- 5% of the chip rate (e.g., 20.48 MHz)

    • The timer period must be configurable by the Wireless Core.

    • The timer priority must be the highest in the system. It must exceed the radio’s IRQ and SPI DMA IRQ priority.

MCU Performance

The following hardware features will impact the speed of execution of a given application.

  1. CPU cores

  • Some CPU cores (e.g. ARM Cortex-M4) may be more or less efficient than others for a given task.

  1. CPU clock speed

  • Running a given CPU core at a higher clock speed will result in faster processing time, which is sometimes required for higher performance applications.

  1. SPI Throughput

  • SPARK transceivers use SPI for all communications with the MCU, whether it is for frame transfers or configuration. It is important to select an MCU with an SPI throughput that can satisfy the application requirements. SPI clock speed, byte interspacing and initial setup time are all dependent on the selected MCU.

  • The maximum and optimal SPI speed for SPARK transceivers is 40 MHz.

  1. MCU architecture

  • Some MCUs have hardware accelerators, multiple cores, direct memory access (DMA) buses for efficient non-blocking data transfers and faster memory zones for code execution.

  • For example, the STM32G473 MCU on SPARK’s EVK1.4 carrier board has CCM (Core-Coupled Memory) where critical code can be copied and executed from without any waiting states leading to faster response and lower execution times.

  • Another example, the STM32U5A5 MCU on SPARK’s Quasar carrier board has ICACHE (Instruction Cache) where instructions from the flash memory can be cached, allowing the processor to execute them more rapidly by reducing the wait states.

  1. Memory Size

  • More memory means more room for code optimization (e.g. inline functions or unrolled loops are usually executed faster but take more space). See Memory section for information about memory size required by the SPARK Wireless Core.

Note

It is assumed that the user has selected a suitable MCU for their targeted application. The focus of this porting guide is on outlining the firmware changes required to support a customer-specific hardware platform which may include an MCU that is different than the ones used on SPARK’s Evaluation Kits.