SPI Implementation

The Serial Peripherals Interface (SPI) article describes how the MCU’s SPI must be configured to work with the SPARK Wireless Core. The BSP requires the following MCU SPI interface configurations:

  • 50 MHz SPI clock or lower

  • Master mode

  • 2-line direction

  • 8-bit data

  • First bit MSB

  • Clock steady state on low (CPOL=0)

  • Clock active on first edge for the bit capture (CPHA=0)

In high data rate applications, the SPI interface could become a bottleneck, so special care must be given to optimize this interface for performance. The SPI peripheral configuration can be found in the BSP top-level file bsp.c. The SPI transfer function implementation can be found in the bsp_radio.c file.

Table 20: Reference: Table 14: SPI Characteristics from the SR1020 datasheet revision 1.1

Parameter

Test conditions

Min

Typ

Max

Unit

SCK period

25

ns

SCK duty cycle

50

%

CS setup to SCK

12

ns

CS hold after SCK

12

ns

MOSI setup to SCK

0.0

ns

MOSI hold after SCK

4.8

ns

MISO delay after SCK

10pF load

7.0

ns

Warning

For multi-byte SPI transfers, there must be an inter-byte spacing of at least 1 SPI clock (SCK) period.

Tip

It is not recommended to use the MCU manufacturers’ peripherals software libraries when it comes to implementing the SPI in the user BSP as they may not be optimized enough. Users are encouraged to write the SPI driver themselves for maximum performances.

The following SPI implementations are required by the Wireless Core:

  1. SPI transfer in full duplex blocking mode.

  2. SPI transfer in full duplex non-blocking mode.

In blocking mode, the CPU will be held until the SPI transaction is completed. In non-blocking mode, the CPU is free to execute other tasks while a DMA resource manages the SPI data transaction.

The Wireless Core needs to control the SPI Chip Select pin, therefore the user BSP must provide functions for setting and resetting the CS. See the Wireless Core article within the porting guide for more information.

During each SPI clock cycle, a full-duplex data transmission occurs. The master sends a bit on the MOSI line and the slave reads it, while the slave sends a bit on the MISO line and the master reads it. This sequence is maintained even when only one-directional data transfer is intended.

The Wireless Core has a mechanism to accumulate Write or Read instructions into a single instruction buffer. When ready, the instruction buffer is transferred to the SPI Data Register where it gets clocked out onto the SPI Bus.

The figure below illustrates some full-duplex SPI data transactions.

../../_images/spi_full_duplex.png

Figure 53: Example of Full-Duplex SPI Transfer

This porting guide does not provide an in-depth explanation of functionalities and mechanisms present in the Wireless Core. Although, the figure above aims at illustrating what someone could expect to see if they are probing the SPI frames with an analyzer.